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High linearity U-band power amplifier design: a novel intermodulation point analysis method Research Article

Jie CUI, Peipei LI, Weixing SHENG,cuijie@njust.edu.cn

Frontiers of Information Technology & Electronic Engineering 2023, Volume 24, Issue 1,   Pages 176-186 doi: 10.1631/FITEE.2200082

Abstract: A ’s linearity determines the emission signal’s quality and the efficiency of the system. Nonlinear distortion can result in system bit error, out-of-band radiation, and interference with other channels, which severely influence communication system’s quality and reliability. Starting from the third-order intermodulation point of the s, the circuit’s nonlinearity is compensated for. The analysis, design, and implementation of linear class AB mm-Wave s based on GlobalFoundries 45 nm technology are presented. Three single-ended and differential stacked s have been implemented based on cascode cells and triple cascode cells operating in U-band frequencies. According to nonlinear analysis and on-wafer measurements, designs based on triple cascode cells outperform those based on cascode cells. Using single-ended measurements, the differential achieves a measured peak power-added efficiency (PAE) of 47.2% and a saturated output power () of 25.2 dBm at 44 GHz. The amplifier achieves a higher than 23 dBm and a maximum PAE higher than 25% in the measured bandwidth from 44 GHz to 50 GHz.

Keywords： CMOS silicon-on-insulator (SOI)     Linearity analysis     Milimeter wave (mm-Wave)     Power amplifier    

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Behavior of Impurities, Defects and Surface Morphology for Silicon and Silicon Based Semiconducting Materials

Tu Hailing

Strategic Study of CAE 2000, Volume 2, Issue 1,   Pages 7-17

Abstract: Since silicon based materials as the alternative material systems have received strong growing interest, the manufacturing technologies and applications of SiGe, silicon-on-insulator (SOI) have been introducedFinally, the author outlooks the future scientific and engineering challenges and opportunities for siliconand silicon based materials envisioned for the sub quarter-micro and nanometer integrated circuits as

Keywords： silicon wafers     epitaxial silicon wafers     SiGe     silicon-on-insulator (SOI)     impurities behavior     defects control    

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Erratum to: Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology

Najam Muhammad AMIN,Zhi-gong WANG,Zhi-qun LI

Frontiers of Information Technology & Electronic Engineering 2015, Volume 16, Issue 5, doi: 10.1631/FITEE.14e0087

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Effects of nano-silicon and common silicon on lead uptake and translocation in two rice cultivars

Jianguo LIU,Hui CAI,Congcong MEI,Mingxin WANG

Frontiers of Environmental Science & Engineering 2015, Volume 9, Issue 5,   Pages 905-911 doi: 10.1007/s11783-015-0786-x

Abstract: The current study investigated the effects of nano-silicon (Si) and common Si on lead (Pb) toxicity,

Keywords： silicon (Si)     lead (Pb)     rice (Oryza sativa L.)     toxicity     accumulation    

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Analysis and design of transformer-based CMOS ultra-wideband millimeter-wave circuits for wireless applications Review Articles

Yi-ming YU, Kai KANG

Frontiers of Information Technology & Electronic Engineering 2020, Volume 21, Issue 1,   Pages 97-115 doi: 10.1631/FITEE.1900491

Abstract: In this paper, four transformer-based ultra-wideband mm-Wave circuits demonstrated in CMOS technologies

Keywords： CMOS     Millimeter-wave (mm-Wave)     Ultra-wideband     Transformer     Low-noise amplifier     Injection-locked fre-quency    

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Computer modeling of crystal growth of silicon for solar cells

Lijun LIU, Xin LIU, Zaoyang LI, Koichi KAKIMOTO

Frontiers in Energy 2011, Volume 5, Issue 3,   Pages 305-312 doi: 10.1007/s11708-011-0155-9

Abstract: A computer simulator with a global model of heat transfer during crystal growth of Si for solar cells is developed. The convective, conductive, and radiative heat transfers in the furnace are solved together in a coupled manner using the finite volume method. A three-dimensional (3D) global heat transfer model with 3D features is especially made suitable for any crystal growth, while the requirement for computer resources is kept permissible for engineering applications. A structured/unstructured combined mesh scheme is proposed to improve the efficiency and accuracy of the simulation. A dynamic model for the melt-crystal (mc) interface is developed to predict the phase interface behavior in a crystal growth process. Dynamic models for impurities and precipitates are also incorporated into the simulator. Applications of the computer simulator to Czochralski (CZ) growth processes and directional solidification processes of Si crystals for solar cells are introduced. Some typical results, including the turbulent melt flow in a large-scale crucible of a CZ-Si process, the dynamic behaviors of the mc interface, and the transport and distributions of impurities and precipitates, such as oxygen, carbon, and SiC particles, are presented and discussed. The findings show the importance of computer modeling as an effective tool in the analysis and improvement of crystal growth processes and furnace designs for solar Si material.

Keywords： computer modeling     silicon     crystal growth     solar cells    

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A 9.8–30.1 GHz CMOS low-noise amplifier with a 3.2-dB noise figure using inductor- and transformer-based

Hongchen Chen, Haoshen Zhu, Liang Wu, Wenquan Che, Quan Xue,hongdoublechen@gmail.com,zhuhs@scut.edu.cn,wuliang@cuhk.edu.cn,eewqche@scut.edu.cn,eeqxue@scut.edu.cn

Frontiers of Information Technology & Electronic Engineering 2021, Volume 22, Issue 4,   Pages 586-598 doi: 10.1631/FITEE.2000510

Abstract: A 9.8–30.1 GHz (LNA) with a 3.2-dB minimum noise figure (NF) is presented. At the architecture level, a topology based on (CG) cascading with a common-source (CS) amplifier is proposed for simultaneous wideband input matching and relatively high gain. At the circuit level, multiple techniques are proposed to improve LNA performance. First, in the CG stage, loading effect is properly used instead of the conventional feedback technique, to enable simultaneous impedance and noise matching. Second, based on in-depth theoretical analysis, the inductor- and -based techniques are employed for the CG and CS stages, respectively, to enhance the gain and reduce power consumption. Third, the floating-body method, which was originally proposed to lower NF in CS amplifiers, is adopted in the CG stage to further reduce NF. Fabricated in a 65-nm technology, the LNA chip occupies an area of only 0.2 mm and measures a maximum power gain of 10.9 dB with −3 dB bandwidth from 9.8 to 30.1 GHz. The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth. The LNA consumes 15.6 mW from a 1.2-V supply.

Keywords： CMOS；跨导提升技术；低噪声放大器；变压器；共栅级    

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Automated optimization technique of CMOS analog cell circuit based on symbolic analysis

Zheng Weishan,Deng Qing,Liu Zhaoxia,Shi Longxing

Strategic Study of CAE 2009, Volume 11, Issue 4,   Pages 50-56

Abstract:

A methodology for automatic design optimization of CMOS analog cell circuits

Keywords： optimization     performance equation     symbolic analysis     genetic algorithm    

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Atomistic understanding of interfacial processing mechanism of silicon in water environment: A ReaxFF

Frontiers of Mechanical Engineering 2021, Volume 16, Issue 3,   Pages 570-579 doi: 10.1007/s11465-021-0642-6

Abstract: The interfacial wear between silicon and amorphous silica in water environment is critical in numerousHerein, reactive force field simulations are utilized to study the interfacial process between silicon

Keywords： silicon     ReaxFF     molecular dynamics     friction     damage    

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Effect of extrusion temperature on the physical properties of high-silicon aluminum alloy

YANG Fuliang, GAN Weiping, CHEN Zhaoke

Frontiers of Mechanical Engineering 2007, Volume 2, Issue 1,   Pages 120-124 doi: 10.1007/s11465-007-0021-y

Abstract: Light-weight high-silicon aluminum alloys are used for electronic packaging in the aviation and space-flightExperimental results show that the density of high-silicon aluminum alloys prepared with this method

Keywords： coefficient     hermeticity     temperature     relationship     air-atomization    

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Laser enhanced gettering of silicon substrates

Daniel CHEN,Matthew EDWARDS,Stuart WENHAM,Malcolm ABBOTT,Brett HALLAM

Frontiers in Energy 2017, Volume 11, Issue 1,   Pages 23-31 doi: 10.1007/s11708-016-0441-7

Abstract: One challenge to the use of lightly-doped, high efficiency emitters on multicrystalline silicon wafers, a novel laser based method for gettering is investigated for its impact on commercially available silicon

Keywords： gettering     multicystaline     silicon     impurities     laser doping    

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Special issue: Technologies for future high-efficiency industrial silicon wafer solar cells

Frontiers in Energy 2017, Volume 11, Issue 1,   Pages 1-3 doi: 10.1007/s11708-016-0436-4

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Cross-layer efforts for energy-efficient computing: towards peta operations per second perwatt Perspectives

Xiaobo Sharon HU, Michael NIEMIER

Frontiers of Information Technology & Electronic Engineering 2018, Volume 19, Issue 10,   Pages 1209-1223 doi: 10.1631/FITEE.1800466

Abstract: respect to traditional Boolean circuits and von Neumann processors, it will be challenging for beyond-CMOSdevices to compete with the CMOS technology.To take full advantage of beyond-CMOS devices, cross-layer efforts spanning from devices to circuits

Keywords： Moore’s law     Energy-efficient computing     Neural network accelerators     Beyond-CMOS devices    

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Erratum to: Enhancing the photoelectrochemical performance of p-silicon through TiO coating decorated

Frontiers in Energy 2022, Volume 16, Issue 5,   Pages 876-877 doi: 10.1007/s11708-022-0832-x

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Effects of taping on grinding quality of silicon wafers in backgrinding

Zhigang DONG, Qian ZHANG, Haijun LIU, Renke KANG, Shang GAO

Frontiers of Mechanical Engineering 2021, Volume 16, Issue 3,   Pages 559-569 doi: 10.1007/s11465-020-0624-0

Abstract: Taping is often used to protect patterned wafers and reduce fragmentation during backgrinding of siliconGrinding experiments using coarse and fine resin-bond diamond grinding wheels were performed on siliconHowever, the PV value, surface roughness, and subsurface damage of silicon wafers with taping deterioratedThe PV value of silicon wafers with taping decreased with increasing mesh size of the grinding wheelThe surface roughness and subsurface damage of silicon wafers with taping decreased with increasing mesh

Keywords： taping     silicon wafer     backgrinding     subsurface damage     surface roughness    

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Title Author Date Type Operation

High linearity U-band power amplifier design: a novel intermodulation point analysis method

Jie CUI, Peipei LI, Weixing SHENG,cuijie@njust.edu.cn

Journal Article

Behavior of Impurities, Defects and Surface Morphology for Silicon and Silicon Based Semiconducting Materials

Tu Hailing

Journal Article

Erratum to: Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology

Najam Muhammad AMIN,Zhi-gong WANG,Zhi-qun LI

Journal Article

Effects of nano-silicon and common silicon on lead uptake and translocation in two rice cultivars

Jianguo LIU,Hui CAI,Congcong MEI,Mingxin WANG

Journal Article

Analysis and design of transformer-based CMOS ultra-wideband millimeter-wave circuits for wireless applications

Yi-ming YU, Kai KANG

Journal Article

Computer modeling of crystal growth of silicon for solar cells

Lijun LIU, Xin LIU, Zaoyang LI, Koichi KAKIMOTO

Journal Article

A 9.8–30.1 GHz CMOS low-noise amplifier with a 3.2-dB noise figure using inductor- and transformer-based

Hongchen Chen, Haoshen Zhu, Liang Wu, Wenquan Che, Quan Xue,hongdoublechen@gmail.com,zhuhs@scut.edu.cn,wuliang@cuhk.edu.cn,eewqche@scut.edu.cn,eeqxue@scut.edu.cn

Journal Article

Automated optimization technique of CMOS analog cell circuit based on symbolic analysis

Zheng Weishan,Deng Qing,Liu Zhaoxia,Shi Longxing

Journal Article

Atomistic understanding of interfacial processing mechanism of silicon in water environment: A ReaxFF

Journal Article

Effect of extrusion temperature on the physical properties of high-silicon aluminum alloy

YANG Fuliang, GAN Weiping, CHEN Zhaoke

Journal Article

Laser enhanced gettering of silicon substrates

Daniel CHEN,Matthew EDWARDS,Stuart WENHAM,Malcolm ABBOTT,Brett HALLAM

Journal Article

Special issue: Technologies for future high-efficiency industrial silicon wafer solar cells

Journal Article

Cross-layer efforts for energy-efficient computing: towards peta operations per second perwatt

Xiaobo Sharon HU, Michael NIEMIER

Journal Article

Erratum to: Enhancing the photoelectrochemical performance of p-silicon through TiO coating decorated

Journal Article

Effects of taping on grinding quality of silicon wafers in backgrinding

Zhigang DONG, Qian ZHANG, Haijun LIU, Renke KANG, Shang GAO

Journal Article